Project at the HAW Hamburg

In 2024, Felix tested various logic gates for their switching time under input signals in the GHz range. The goal was to implement logical AND, OR, and NOT gates using CMOS technology. For this setup, low-level N-MOS and P-MOS MOSFETs were used, which together form the well-known CMOS circuit.

In practice, it became apparent that when attempting to feed a GHz signal into the constructed measurement circuit, the impedance of the cables as well as parasitic inductances and capacitances caused signal reflections in the lines, along with high turn-on and turn-off currents in the MOSFETs.

The experiment was documented and then repeated at 300 MHz. In this case, the measurements showed that the switching on and off times of the MOSFETs sometimes differed by a multiple from the manufacturers’ specifications

Problem Statement

Logical gates are typically integrated into microchip circuits, where CMOS components are built thousands of times smaller and more compactly than in the assembled test circuits. The switching behavior, especially of logical gates, can therefore only be transferred to a limited extent from microscopic components to centimeter-scale structures, since the influence of material properties and propagation delays between individual components is too significant.

MOSFETs

The following MOSFETs were tested both for the simulation and for the subsequent practical measurements:

• N-MOS: 2N7000 (TO-92 package)

• P-MOS: ZVP2106A (TO-92 package)

The models were simulated in LTspice and were also created or parameterized manually.

2N7000
.model 2N7000 VDMOS (Rg=25 Vto=2.55 Rd=0.37 Rs=1m Rb=0.6 Kp=0.36 Cgdmax=20p
Cgdmin=2.8p Cgs=17p Cjo=12p Is=1u Ksubthres=.1 Vds=60 Ron=1.2 Qg=1.4n)

ZVP2106A
.model ZVP2106A VDMOS (pchan Rg=62.5 Vto=-2.5 Rd=1.25 Rs=1m Rb=2.5 Kp=0.18
Cgdmax=35p Cgdmin=7p Cgs=80p Cjo=60p Is=0.5u Ksubthres=.1 Vds=-60 Ron=5
Qg=2.8n)